With the rapid development of ultra-large-scale integration, the fabrication process of integrated circuits becomes more and more complex and sophisticated. To improve integration degree and to reduce manufacturing cost, the number of semiconductor components per unit area in the chip increases. Planar wiring has been difficult to meet the demand of high-density distribution of semiconductor components. Multi-layer wiring technology is performed to use vertical space of the chip to further improve the integration degree of the devices. However, using the multi-layer wiring technology can cause rough surface of the silicon wafer, which may affect patterning processes. Therefore, to realize the multi-layer wiring structure, each layer of the semiconductor structure first needs to have a high level of flatness; and the semiconductor structures on the wafer also need to be planarized.
A chemical mechanical polishing (CMP) process is one of the most common planarization processes. The planarization efficiency of the chemical mechanical polishing process is high, and CMP process has become an indispensable semiconductor process technology.
However, after performing the planarization process onto semiconductor structures formed by existing fabrication techniques, the wafer surface is prone to scratches. The disclosed device structures and methods are directed to solve one or more problems set forth above and other problems.